No abstract

No abstract

A low-power low-voltage direct digital frequency synthesizer is presented in this paper. With the proposed efficient ROM compression method and other ROM reduction techniques, a compression ratio of 236 is achieved. Through low-power techniques at various design levels: low-voltage (2-V) operation, ROM reduction, the proposed parallel architecture, static conventional CMOS gates, and true single phase clocking scheme, an unparalleled power performance is obtained. The final chip is successfully fabricated and guaranteed to function 100% correctly at 62.5 MHz.