In the recent year, many other new circuits are proposed using less number of transistors with less delay and very low power requirement. An adder with 10 transistors an adder with 8 transistors do not give full swing outputs for all input combinations and there is difference in output level for different combinations and these circuits have very low driving capabilities. Some other circuits are also proposed in but they do not give full swing output for all input combinations and power requirement is more. And these adders are not considered due to they do not provide full swing output. The Full Adder is designed using hybrid CMOS logic style by dividing it in three modules so that it can be optimized at various levels.[1] First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. It also consumes minimum power and provides better delay performance. Second module is sum circuit which is also a XOR circuit and uses carry input and the output of the first module as input to generate sum output. Third module is a carry circuit which uses the output of the first stage and other inputs to generate carry output. In the new full adder design new full adder circuit is proposed which reduce the power consumption, delay between carry out to carry in and PDP by 12 to 100%. Simulations are carried out on HSPICE using TSMC 0.12µm CMOS technology. So far designing the high performance arithmetic circuits minimization of the power and delay of the full adder circuit is required. This gives a new carry select full adder using this cmos full adder.