In recent years, technology has embraced the use of Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistors (JL DGMOSFET) to reduce Short Channel Effects (SCEs). This research presents a novel JL DGMOS-FET based on a highly doped N-type SiGe in which an III-V compound material is used at source regime. The III-V compound material GaSb with higher mobility and higher injection velocity is used as source material, whereas SiGe is considered for both channel and drain materials to produce a higher output current and low leakage current for the N channel JL DGMOSFET. In addition, high-k dielectric material HfO 2 is employed to improve the controllability of the gate at 20 nm channel length. Different parameters, such as I d , SS, g m , TGF, I on /I off ratio, C gs , and f T of a Symmetric JL DGMOSFET are studied and compared to existing works. The comparison shows that the proposed JL DGMOSFET outperforms the existing state of knowledge. The analysis is also being extended by including the trap charge for the symmetric JL DGMOSFET. Parametrically, the asymmetrical structure is finally studied. The proposed structure yields a higher I d of 40 mA, SS of 60.25 mV/decade, g m of 0.148 A/V, TGF of 3.69 V-1, I on /I off ratio of 3.41 × 10 13 , C gs of 3.78 × 10 −16 F and f T of 1.19 × 10 13 Hz, hence indicating an improved RF and DC analysis. K E Y W O R D Sasymmetric, cut-off frequency (f T ), donor traps, acceptor traps, gate drain capacitance (C gd ), gate source capacitance (C gs ), high-k dielectric, I on /I off ratio, junctionless double gate (JL DG) MOSFET, subthreshold swing, symmetric, transconductance (g m ), transconductance generation factor (TGF)

Better figure of merits (FOMs) have been achieved by using III-V compound material based junctionless double gate metal-oxide semiconductor field-effect transistors (JL DG-MOSFETs), and a thorough analysis of the device’s performance over temperature has been performed using a highly N-doped GaAs-based JL DG-MOSFET using III-V compound material GaSb. GaSb, a compound material, is employed as the source material, which is well known for its greater mobility and injection velocity property with GaAs as the channel and drain materials, to obtain more output current and less leakage current due to the development of hetero structure (GaSb-GaAs) at the source-channel interface. The dielectric material HfO2 with a high k value is utilized to reduce the gate tunneling effects of electrons and enhance the control of the gate at the 20 nm channel length. Primary and auxiliary gates are taken to include ipact ionization on drain side for reducing the Subthreshold-swing. Numerous characteristics of a DG JLMOSFET, such as Id, SS, gm, TGF, Ion/Ioff, Cgs, and fT, GFP, TFP, GTFP are explored and compared with a silicon based material. The proposed structure shows an improved results comparing to the earlier model with Id of 117 mA, SS of 15.08 mV decade−1, gm of 0.62 A V−1, TGF of 38.8 V−1, Ion/Ioff ratio of 1.89 × 10 13, Cgs of 5.86 × 10 −16 F, fT of 2.05 × 10 15 Hz, GTFP of 1.81 × 10 17 Hz/V for the improvement of FOM in RF and DC analysis.

No abstract

The logic performance of a hybrid complementary-metal-oxide-semiconductor (CMOS) circuit based on a novel technology known as a junction-less transistor constructed with high-K and III-V compound material junction-less-double-gate MOSFET (JL-DG-MOSFET) for ultra-low power applications is analyzed. The CMOS circuit is constructed by using a Ge-based P-MOS and GaAs based N-MOS to analyze different performance metrics of inverter such as noise margin, voltage transfer characteristics, transient response, gain, frequency response, and propagation delay using mixed mode analysis. The aforementioned characteristics of the proposed inverter are analyzed and compared with an Si-based CMOS inverter and we observed that the proposed structure shows an improved circuit performance over Si-based CMOS circuit. Consequently, the work is also extended to the design and performances of universal logic gates. The aforementioned N-MOS structure has a higher drive current of 1.3 mA, gm of 5.9 mS, gd of 20.8 mS, SS of 64 mV/Decade, and DIBL of 23mV/V, whereas the Ge based P-MOS structure yields drive current of 0.7 mA, gm of 1.5 mS, gd of 5.6 mS, SS of 95 mV/Decade, and DIBL of 21mV/V. The hybrid C-MOS structure has a higher unity-gain bandwidth of 1100GHz and lower propagation delay of 3.1ps

No abstract