No abstract

In this work a compact microprobe for advanced chip-inspection applications is introduced. The probe features integrated photoconductive switches for Terahertz pulse generation and detection. Device application is demonstrated for contact-free high-resolution time-domain reflectometry measurements at silicon-chip test structures

Many semiconductor companies are currently engaged in 3D system integration. The assembly of 3D compliant chips becomes a vital factor of the 3D application success and reliability. Major challenges are provided by very low chip thickness, large die size, small interconnect diameter and pitch. Diverse 3D assembly technologies and methods are currently under investigations which address these specific technical challenges. Stable and volume capable assembly processes must be developed in order to manufacture such products in future with reasonable cost. Wafer-to-wafer (W2W) assembly is not yet recommended for most of the advanced 3D applications since it still suffering from too high yield losses what would translate into unacceptable W2W stack yield. For that reason the die-to-die (D2D) assembly is considered as the more efficient way for the time being. For that reason we?re developing integrated assembly and test concepts on 300 mm wafer size to evaluate and validate various assembly technologies regarding to their capabilities with respect to interconnect materials, dimension, pitch and I/O density

The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.