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Purpose The control of a quadrotor unmanned aerial vehicle (UAV) is a challenging problem because of its highly nonlinear dynamics, under-actuated nature and strong cross-couplings. To solve this problem, this paper aims to propose a robust control strategy, based on a concept of active disturbance rejection control (ADRC). Design/methodology/approach The altitude/attitude dynamics of a quadrotor is reformulated into the ADRC framework. Three distinct variations of the error-based ADRC algorithms, with different structures of generalized extended state observers (GESO), are derived for the altitude/attitude trajectory-following task. The convergence of the observation part is proved based on the singular perturbation theory. Through a frequency analysis and a quantitative comparison in a simulated environment, each design is shown to have certain advantages and disadvantages in terms of tracking accuracy and robustness. The digital prototypes of the proposed controllers for quadrotor altitude and attitude control channels are designed and validated through real-time hardware-in-the-loop (HIL) co-simulation, with field-programmable gate array (FPGA) hardware. Findings The effects of unavailable reference time-derivatives can be estimated by the ESO and rejected through the outer control loop. The higher order ESOs demonstrate better performances, but with reductions of stability margins. Time-domain simulation analysis reveals the benefits of the proposed control structure related to classical control approach. Real-time FPGA-based HIL co-simulations validated the performances of the considered digital controllers in typical quadrotor flight scenarios. Practical implications The conducted study forms a set of practical guidelines for end-users for selecting specific ADRC design for quadrotor control depending on the given control objective and work conditions. Furthermore, the paper presents detailed procedure for the design, simulation and validation of the embedded FPGA-based quadrotor control unit. Originality/value In light of the currently available literature on error-based ADRC, a comprehensive approach is applied here, which includes the design of error-based ADRC with different GESOs, its frequency-domain and time-domain analyses using different simulation of UAV flight scenarios, as well as its FPGA-based implementation and testing on the real hardware.

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