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Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.