In this paper, we propose an efficient algorithm for computing architecture for highperformance Inter Prediction SAD encoder. HEVC Motion Estimation(ME) Inter prediction is a process of searching for the currently high prediction block (PU)

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In this paper, we propose an efficient algorithm for computing architecture for high-performance Inter Prediction SAD encoder. HEVC Motion Estimation(ME) of the Inter prediction is a process for searching for the currently high prediction block PU and the correlation in the interpolated reference picture in order to remove temporal redundancy. This paper proposes a new algorithm which reduces the computational complexity by reusing the 4x4 SAD operation in full search to reduce the amount of calculation and computational time of the Inter Prediction. The proposed algorithm is applied to an HEVC standard software HM16.12. There was an improved operational time of 61% compared to the traditional full search algorithm, BDBitrate was decreased by 11.81% and BDPSNR increased by about 0.