This paper presents a new approach for generating saturation constraints and DC performance expressions for analog integrated circuits. It also proposes a generalized method to develop AC performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes very less time and does not require any manual intervention. The proposed method for AC performance expression generation is built on two levels of abstraction of a circuit. At the higher level, referred as macromodel, circuit performance metrics are modeled as function of device parameters such as transconductance (g m ), drain conductance (g d ), small-signal parasitic capacitances and overdrive voltage (V ov ). Whereas, at lower level of the abstraction the device parameters are monomial functions of device sizes and their biases. The two-level abstraction helps to develop technology independent performance model of a circuit. Whereas, the technology dependency is captured through device models. The proposed methods are applied to two well-known CMOS op-amp topologies namely, twostage and folded-cascode to generate saturation constraints, DC and AC performance expressions. With the developed constraints, both the circuits are designed through GP based circuit optimization in a 0.18 µm UMC technology. Performances of both are verified at their final design points.

No abstract

No abstract

A knowledge based approach empowered by geometric programming (GP) for analog circuit synthesis and sizing is presented. Analog circuit performance specification is mapped to various building blocks of a circuit topology. Then, the topology is modified according to the design rules in the library. Each modification is validated over two steps. In the first step, dc performance constraints are introduced. If qualified, ac performance constraints are introduced. Validation over two steps helps to gradually close in on input specifications removing any undesired correction made initially. It results in faster convergence.

Over the years, as system on chip is increasingly incorporating analog functionalities, there is a need of a tool, which can automate the analog topology selection and sizing flow. We develop one efficient methodology to automatically select the best topology given only the user specifications. The proposed topology selection is a multilevel screening process inherited from geometric programming (GP) by sequentially introducing sub-sets of requirements. This helps to prune out unfit topologies at early stage and hence not costing much computational effort. Use of GP ensures fast convergence with optimal solution. Apart from the speed advantage, compared to the existing literature, methodology has better representation of topology performance expressions. We propose to use two levels of performance expressions. First one is technology independent and the second one is technology specific. This bifurcation of performance expressions help in quick technology migration. Third contribution is automatic node expression generation which are required for dc performance evaluation. The proposed methodology is used for selecting optimal error amplifier topology for low dropout regulator (LDO).