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SUMMARYIn contrast with the conventional split loop digital phase lock loop, a new loop is presented in this paper that differs from the earlier version principally by design aspects. It incorporates an additional phase modulation input along with its frequency modulation input in the digital controlled oscillator. It is capable of eliminating the deleterious effects of rounding and truncation error with faster signal accusation. Higher loop stability is also achievable using the new split loop digital phase lock loop. Furthermore, radio frequency filtering is done using an In phase and Quadrature phase (IQ) voltage controlled oscillator to avoid interaction between the loop filter and the radio frequency filter. Copyright © 2011 John Wiley & Sons, Ltd.

This paper proposes a new split digital phase lock loop (DPLL) in the presence of additive wideband Gaussian noise. The proposed new loop incorporates an additional phase modulation input along with its frequency modulation input in the digitally controlled oscillator of the loop. The present loop eliminates the deleterious effects of wideband Gaussian noise. A better output signal-to-noise ratio is achieved using the new split-loop DPLL. In the design of the loop, the interaction between the loop and the radio frequency filters is avoided by using an in-phase and quadrature-phase digitally control oscillator. The proposed split-loop DPLL is simulated using MATLAB (The MathWorks, Natick, MA, USA)/Simulink environment and System Generator, a tool from Xilinx (Xilinx, Inc., San Jose, CA, USA) used for field programmable gate array design, as well as implemented on a Spartan 3E Starter Kit board. The design is implemented on field programmable gate array using the VHDL [Very High Speed Integrated Circuit (VHSIC) Hardware Description Language] language on Xilinx ISE 13.1. The proposed split-loop DPLL proves to be better than the conventional split-loop DPLL from the standpoint of the settling time, the peak time, the rise time, and the peak overshoot as well as from the standpoint of the BER performance for a typical binary phase-shift keying system and validates against the MATLAB/Simulink results. PERFORMANCE OF A NEW SPLIT DIGITAL PHASE LOCK LOOP 1109 I H.´/H.´ 1 /´ 1 d´(6) where B i = 2 is the bandwidth of the input signal. Using [8], we can derive the noise bandwidth of the new split-loop DPLL similarly as in [2], B L, split-loop DPLL B i = 2 D

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