Abstract. Arithmetic operations are important and most commonly used functions in VLSI applications. 1-single bit full adder digital circuit is the building block that performs the operations such of addition, subtraction, multiplication, etc. Designing, Implementation of single bit full adder circuits in nm submicron process and 45nm deep submicron process are evaluated in this paper. Three adder circuits considered are Conventional adder, Mirror adder and transmission gate logic adder are evaluated in this paper. Schematic and Layout of all three adder circuits in both micron process are administered with D.C and pulse inputs. Evaluation of powerdelay product, parasitic capacitance and comparison between performance of adder circuits in both process are asserted. The adders are Modeled using EDA-Electric tool and LT spice simulation software.

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