A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This paper discusses the BiCMOS design improvements used for the phase accumulator and the phase-toamplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 µm technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm 2 .

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Abstract-The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and onchip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This operational amplifier provides both low noise and high gain performances. This operational amplifier has an area of only 660×250 µm 2 with an equivalent input noise floor of only 1.1 nV/ √ Hz square root at 10 kHz. The measured noise characteristics (versus total power consumption) are better than those of most operational amplifiers commonly adopted in low-frequency noise measurements. The AC gain is 83 dB and the unity gain bandwidth is 210 MHz, with a total current consumption of 18 mA at 2.5 V supply voltage.

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