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Design solutions of domestic VLSI were obtained as a result of the application of computeraided design tools of a foreign supplier (CAD Synopsys, Cadence Design Systems and Mentor Graphics), based on standard libraries of PDK elements (Project Design KIT) of factories and IC-modules also supplied mainly by foreign companies. As a rule, the developer does not have its own production facilities, using the services provided by foreign factories (fablesscompanies). Due to this fact, relevant are the studies aimed at the development of a complex of measures, excluding the possibility of unauthorized changes into IC, i.e. protection of projects against intentional hardware and technology violations made during the formation of the control information for handing it over to the production facility and/or in case of IC manufacture at the factory. This paper considers this task from the standpoint of the analysis of the methodology of design for testability (DFT), i.e., a complex of measures that provide obtaining solutions at the design stage. The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures. It was proposed, inter alia: 1) to analyze the libraries of standard elements used in the project with full disclosure of their specifications; 2) to create nodes with the physical non-cloning function in the projects on the basis of the libraries of standard elements in models and analysis programs; 3) to analyze IP modules used in the project with the maximum disclosure of structure, methods and algorithms for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and programs both within SoC cores and at the level of system buses; 5) to develop at the design stage and to apply during tests a technique of special hardware measurements of parameters of the manufactured circuits and analysis of their results, inter alia, according to measurements of delays in distribution of signals and/or buses current consumption.Проектные решения отечественных СБИС получены в результате применения инструментов автоматизированного проектирования зарубежного поставщика (САПР Synopsys, Cadence Design Systems и Mentor Graphics) на основе библиотек стандартных элементов PDK (Project Design KIT) фабрик и IP-модулей, поставщиками которых также являются в основном зарубежные компании. Как правило, компания-разработчик не имеет собственных производственных мощностей, пользуясь услугами иностранных фабрик (fabless-компании). В этой связи актуальными являются исследования по созданию комплекса мер, исключающих возможности внесения несанкционированных изменений в интегральные схемы (ИС), т. е. защиты проектов от намеренных аппаратных и технологических нарушений, вносимых при формировании управляющей информации для передачи на производство и/или при изготовлении ИС на фабрике. В данной работе эта проблема рассматривается с по...

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