SUMMARYA systematic method for deriving CFA-based all-grounded-capacitor filters from current mode RLC prototype ladder has been given. It is based on the operational simulation of node voltages and branch currents. It is extended to a voltage-mode ladder. These filters employ a minimum number of capacitors and minimum total capacitance. In some cases, all the capacitors can be made of equal value. Such filters are suitable for fabrication in integrated circuit technology. Illustrative examples for realizing generic filters are included with their simulation results.

No abstract

In the conventional method, a truth table (TT) is prepared from the specified logic function. Then it is expressed as the sum of min terms corresponding to the rows in which 1 appears. Finally, this function is further reduced using the Boolean identities. Thus, all the simplifications are concentrated at one place after the TT. This procedure does not always lead to the minimal realization. This paper deals with the minimal realization of logic function using TT in which TT is reduced successively by one variable at a time till all the variables are exhausted. The simplification is carried out, instead at the end of the truth table, at the end of each step of TT reduction. The method is shown to be systematic, and definitely leads to the minimal function. It is simpler in operation than that based on only Boolean identities, Karnaugh map and Quine-McClusky methods, and can handle any number of variables. It is explained with several examples. It is worth introducing as an improvement over the classical TT method in class room teaching.

No abstract