The fast growth of the power density in integrated circuits has made area and power dissipation as the vital design measures. In this paper, several different flip-flop topologies are analyzed and an area, power efficient flip-flop design is proposed. This design overcomes the power dissipation due to the large precharge node capacitance, with reduced number of transistors. The comparative power analysis and performance improvements indicate that the proposed design is suitable for high-performance digital designs where the area and power dissipation is of major concern. The simulation results are verified using tanner v7.0 tool. The performance comparisons are made using CMOS0.18µm technology.

Power consumption and energy efficiency plays a vital role in sequential circuit design. Clock gating is a technique that is used to reduce the dynamic power consumption of idle modules. Usage of Dual Edge Triggered Flip-flop (DETFF) is an efficient technique since it consumes half the clock frequency and less power than Single Edge Triggered Flipflops (SETFF's). Integrating clock gating technique with DETFF reduces the power consumption further, but it leads to asynchronous data sampling problem (change in output between clock edges). In this paper, two methods have been used to eradicate asynchronous data sampling problem and their power analysis has been estimated. In order to reduce the power consumption further, a new design has been proposed for DETFF. Based on the new design, two methods have been implemented using Tanner EDA tool. The performance comparison is made using CMOS 0.18µm technology.