If, upon substituting signal lines for all flip‐flops in a sequential circuit, the test generation problem for this sequential circuit can be reduced to the problem of test generation for a combinational circuit, one may call this sequential circuit a sequential circuit allowing test generation with combinational test generation complexity. For example, balanced structures are characterized by this feature. The authors introduce a new wider class called internally balanced structures. The sequential circuits can be classified by the circuit structure as follows: {sequential circuits of acyclic structure} ⊃ {sequential circuits of internally balanced structure} ⊃ {sequential circuits of balanced structure}. It is shown that, as opposed to sequential circuits of acyclic structure, which do not necessarily allow test generations with combinational test generation complexity, sequential circuits of internally balanced structure and balanced structure allow test generation with combinational test generation complexity. On the other hand, it is shown that finite state machines (FSM) can be grouped by their realization possibility as follows: {FSM allowing realization as acyclic structure} = {FSM allowing realization as internally balanced structure} ⊃ {FSM allowing realization as balanced structure}. Finally, the authors discuss using features of the internally balanced structures which allow test generation with combinational test generation complexity for implementing designs for testability based on the new partial scan approach, and for reducing the test generation time in sequential circuits. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 11–21, 1997

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In this paper, we theoretically and experimentally show the eectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we i n troduce a method of extended partial scan design, which replaces part of not only ip-ops by scan ip-ops but also wires by bypass ip-ops in a sequential circuit, and propose a method of extended partial scan design based on internally balanced structure. Experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented with low area overhead.