No abstract

We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of the sequential logic circuits.Spatio-temporal correlations are totally considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on the circuit size and it depends only on the user-specied unrolling number, which is usually 2 or 3.Experimental results show that our approach is 100-times faster than the logic simulation and 10-times more accurate than the previous approach which ignores all correlations.