We present a scalable parallel memory architecture with skew scheme. It achieves equal conflict-free vector access strides among different numbers of memory modules. With previous skew schemes, conflict-free strides depended on the number of memory modules. Therefore the skew scheme should be independent of the number of memory modules. We analyze two kinds of cause of conflicts, permanent concentration in the limited memory modules and transient concentration in one memory module. The conflict-free strides are proved to be independent of the number of memory modules by solving two concentrations separately, The strategy is to increase the interval of the shifting address assignment of the memory modules in order to reduce the permanent concentrations, and to provide buffers for each memory module in accordance with this interval in order to absorb the transient concentrations. The skew scheme uses the same period for memory systems with different numbers of memory modules. Consequently, scalability for conflictfree strides can be realized, independent of the number of the memory modules.

This paper discusses the storage control unit of the Hitachi S-3800 supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four shared-memory multiprocessors.This storage control unit is distributed to the V-SCS (vector-processor-side storage control units) and the M-SCS (main-storage-side storage control units), and achieves 128 gigabytes per second of total memory throughput. This distributed storage control unit supports scalability with increases in the number of processors and segmented parallel pipelines, simply by reconnecting the flat cables between the V-SCS and M-SCS. The distributed storage control unit also facilitated high sustained memory throughput for all types of vector-load and -store instructions. It features three new storage control schemes. (1) A hierarchical request-identification-number assignment scheme, which allows independent parallel memory access control in the V-SCS and M-SCS, This also enhances the indirect memory access performance.(2) A multistage address modification scheme, which achieves conflict-free constant-stride parallel memory access in both the V-SCS and M-SCS.(3) An instruction-based variable priority scheme, which achieves stable high memory throughput independent of other programs executed on the other processors. Results of performance measurements show the benefit of these schemes in the scalable distributed storage control unit for the S-3800 series.

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