Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

We report on control of growth directions of InAs nanowires on Si substrate. We achieved to integrate vertical InAs nanowires on Si by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Crosssectional transmission electron microscope and Raman scattering showed that misfit dislocation with local strains were accommodated in the interface.

We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm(2)), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III-V NWs on Si.

Highly uniform GaAs/GaAsP coaxial nanowires were prepared via selective-area metal organic vapor phase epitaxy. Photoluminescence spectra from a single nanowire indicate that the obtained heterostructures can produce near-infrared (NIR) lasing under pulsed light excitation. The end facets of a single nanowire form a natural mirror surface to create an axial cavity, which realizes resonance and give stimulated emission. This study is a considerable advance toward the realization of nanowire-based NIR light sources.

We report on the fabrication of GaAs hexagonal nanowires surrounded by ͕110͖ vertical facets on a GaAs ͑111͒ B substrate using selective-area ͑SA͒ metalorganic vapor-phase epitaxial ͑MOVPE͒ growth. The substrate for SA growth was partially covered with thin SiO 2 , and a circular mask opening with a diameter d 0 of 50-200 nm was defined. After SA-MOVPE, GaAs nanowires with a typical diameter d ranging from 50 to 200 nm and a height from 2 to 9 m were formed vertically on the substrate without any catalysts. The size of the nanowire depends on the growth conditions and the opening size of the masked substrate. A possible growth mechanism is also discussed.