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ABSTRA CT-VLSI system compiler which generates highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms is described here. It consists of several stages to convert processing algorithms into suitable one for VLSI implementation.In this paper, an extended modularization and a placement of general digital signal processing algorithms are proposed as the parts of onr VLSI system compiler. A new modularization algorithm is presented, which will homogenize operations in DSP algorithms of the wider input class than before. Placement algorithm is newly developed, which embeds inner-product processors with requirement of random interprocessor communications into rectangular processor array without losing inherent highly parallel processing natures.

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