Pentacene Organic Thin-Film Transistor (OTFT) integrated withColor Twisted Nematic Liquid Crystals Display (CTNLCD) has been developed. This display used photolithography, pentacene deposition, color filter and TNLC. In addition, we successfully develop the OTFT passivation layer process to avoid the damage of TNLC. Above these processes are integrated to manufacture the 3 inch CTNLCD panels with 64×128 pixels.

We successfully fabricated 5-inch organic thin film transistors array with 320×240 pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing.The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 cm^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 5 inch 320×240 OTFT-EPD was fabricated. All of process temperature in 10×10 OTFT-EPD is lower than 150 . The pixel size in our panel is 300 µm × 300 µm, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.

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We successfully fabricated 4.7-inch organic thin film transistors array with 320×240 pixels on flexible substrate. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.015 cm 2 /V-s, 1.1 V/dec, 10E6 and -3.2 V. After laminated Sipix electrophoretic media on OTFT array, a panel of 4.7 inch 320×240 OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than 130 . The pixel size in our panel is 300 μm × 300 μm, and the aperture ratio is over than 50 %. The OTFT channel length and width is 20 um and 200um, respectively. The operation voltages used on the gate bias is -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages used on the source bias are -20 V, 0 V, and 20 V during display media operation.

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