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This paper describes an efficient technique for the design of fault-secure VLSI circuits based on differential cascode voltage switch (DCVS) logic. We propose a new synthesis method for constructing DCVS circuits with a near-optimal transistor count based on binary decision diagrams (BDDs). The time and memory resources required are very low, making the technique practical even for PC-based synthesis tools. This method is the basis for a CAD tool that allows automatic synthesis of fault-secure circuits based on the DCVS technology. We finally present an improved design and implementation of a 2's complement serial/parallel multiplier as an application of the proposed technique and algorithm.

This paper presents an integrated CAD system for synthesizing high‐performance dual rail circuits using DCVS logic. The proposed techniques exploit ROBDDs to provide efficient DCVS trees that fulfill the design rules and constraints. Sharing of common transistor structures is examined to decrease further the overall device count and chip area by improving the wirability of DCVS circuits. This is accomplished by generating a common variable ordering that permits identification of common subcircuits and simplification of routing procedures by enhancing straight‐line wiring of input signals. The paper also presents the integration steps that are undertaken for importing the developed tools into Alliance CAD system, in order to provide a complete and consistent DCVS circuits synthesis environment and methodology. Moreover, experimental results showed that the proposed algorithms, which are time and memory efficient, produce near optimal device counts improving placement and routing procedures. The integrated design framework, which is available for academic and research purposes, has been employed to synthesize, simulate and layout a programmable 16‐bit serial/parallel multiplier as a complete DCVS circuit synthesis example. © 1998 John Wiley & Sons, Ltd.