Abstract:In the paper a Sugeno architecture based hardware implemented neuro adaptive inference system's training algorithm is presented. The block diagram of the neuro-adaptive inference system output computing implemented in hardware is discussed, and the implementation in reconfigurable circuit of real-time parameter tuning is presented. The proposed system functionality based on measurements achieved is demonstrated. The resulted architecture has a very high processing speed, and the parameter adaptation works in parallel with the output processing. The proposed architecture can also be used for different training algorithms' development.

In the paper the implementation on reconfigurable hardware of a Sugeno type neuro adpative fuzzy inference system is proposed to be presented. The pipeline and parallel pipeline architecture play an important role in modelling the algorithm for the FPGA based implementation. In order to design the pipeline-parallel model of the controller two different methods were used: high level synthesis tool respectively System Generator. Some of the inference systems sub-modules were implemented in VHDL. The proposed hardware model's processing speed is very high, allows the controller to be used in real-time applications.

Abstract:The purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.

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