The technology of vertical integration using Through Silicon Vias (TSVs) now is mature for commercial products with a smaller form factor, better performance, less power consumption and lower cost. This paper addresses two challenges faced with the design using vertical integration. First, methods for the characterization of the physical behavior of the new interconnect structures are described. Second, since issues of reliability and thermal management become more important and difficult and the design space is drastically larger, new early stage design tools are needed. A new floorplanning flow is introduced which supports the cost and performance optimized implementation of digital systems in a stack.