High performance multiprocessors generally require a very complex underlying hardware. This applies notably to shared memory systems, where the communication grain is fine and hence low latencies are critical. In this papel; we describe the prototype of a multiprocessor network which is based on low-cost standard technology. We point out the main dificulties encountered during the design, and we demonstrate our solutions. While accepting a number of speed-versus-cost trade-offs, the resulting system remains within a close range of an optimal design.

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