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A nove linearization circuit for a tunable BiCMOS transconductor based on the emitter degeneration of bipolar devices will be analyzed. The transconductor Is suitable for highfrequency continuous-time filter implementations because of the large value of the gm/I ratio and its easy of tunability. An integrator cell with a unity gain bandwidth up to 80MHz can be realized with capacitive load as large as 3pF (resulting in a reduced sensitivity to parasitic effects) and a power consumption of about 3.5mW. An extended tuning range can be achieved through the proposed linearization circuit that reduces the THD in the lower part of the tuning range. SPICE simulation results are presented comparing the classical solution with respect to the linearized one: the input stage performs an output current THD less than 1% for an input differential signal up to 500mVpp over an almost 1O:l tuning range.

A PRML Reamrite IC operating up to 450MbitIs is presented. The chip implements a 16-state EPR4 Parity Check Time Variant Viterbi detector and a digital servo. A 2426 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35pn BiCMOS technology with a die size of 13 mm2 (step and repeat) and dissipates 1.9 W (in Read Mode) at 450MbiUs.

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