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A system-centric, fully-hicrarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than SO0 million packets per second. Electrical and physical design methods for one IC are described, -76M transistors are integrated in a 130nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.

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New optimized 2x2 slotted array antenna is designed using HFSS to operate at 28.1 GHz, using RT6010 substrate with height of 1.6 mm, tangent loss of 0.0023 and dielectric constant of 10.2 and overall dimension of 12x12 mm 2 , for 5G mobile applications. The 2x2 slotted linear array antenna achieved a high gain of 18.3 dB at 28.1 GHz with 10 dB bandwidth of 1.39 GHz, and with 83.21% of size reduction.