In this paper, a VLSI architecture of a reducedcomplexity K-best sphere decoder is designed, which aims to solve the 4 × 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.