Abstract:The high speed conversions are needed in the faster analog -to-digital converters. The accuracy of comparators is defined by its power consumption and speed. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. Conventional dynamic latched comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. The proposed comparator System has lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. In the dynamic Double tail comparator the simulation in a CMOS technology. In the Proposed dynamic Double tail comparator System both the power consumption and delay time will be significantly reduced. The maximum clock frequency of the proposed comparator can be reduced at modified supply voltages.