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A new sigma-delta architecture employs feedforward topology with digital summing. The feed-forward architecture reduces the signal swings of the integrators and hence modulator distortion while digital summing eliminates the need for a summing op-amp and makes the design more robust to comparator offsets. Applying this architecture to a 2-2 cascade ADC, we can achieve a 12b resolution over a 10MHz signal bandwidth with a sampling rate of 160 MSamples/sec. The topology is especially attractive for low-power and lowvoltage applications.

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