A novel electronically tunable mixed-mode universal biquad by using four single-output and one dual-output-operational transconductance amplifiers, two grounded capacitors is proposed. The proposed circuit has ability to realize voltage, current, transconductance, and transresistance mode, and can the following advantageous features: (i) realization of low-pass, band-pass, high-pass, notch, and all-pass filter responses from the same configuration, (ii) employment of only grounded capacitors ideal for integrated circuit implementation, (iii) orthogonal controlling of x o and Q for easily electronic tunability, and (iv) low active and passive sensitivity performance. Finally, to verify our architecture, we have designed this analog filter chip with TSMC 0.35-lm 2P4M CMOS technology. This chip operates to 1 MHz and consumes 30.95 mW. The chip area of the analog filter is about 0.823 mm 2 .

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A switch-embedded opamp-sharing multiplying digital-to-analogue converter (MDAC) with dual-input-differential-pair operational transconductance amplifier (OTA) is proposed to eliminate the non-resetting and successive-stage crosstalk problems in the conventional opampsharing technique. A 10-bit 80 MS/s pipelined analogue-to-digital converter (ADC) is implemented in a 0.18 mm CMOS process by using the proposed MDAC. Compared with a traditional opampsharing ADC, the measured signal-to-noise ratio is improved from 55.9 to 60.1 dB and the spurious free dynamic range is improved from 66 to 76 dB without any additional power or area consumption or clock phase.Introduction: Applications used in many electronic systems, such as video decoder and wireless communication, require high-resolution low-power analogue-to-digital converters (ADCs). One of the most efficient ways to save power is opamp-sharing between successive pipelined stages. However, that is achieved at the cost of resolution reduction, since the opamp-sharing ADC has two serious problems. First, because the opamp input summing node is never reset, every input sample will be affected by the error voltage stored on the input capacitor due to the previous sample. Thus it suffers from the memory effect, which can be considered as a kind of offset [1]. Secondly, there is a potential crosstalk path between two successive stages caused by the parasitic capacitors of switches that are used to implement opamp sharing. The signals in the current and successive stages, which appear at input nodes of the shared opamp, will influence each other through the crosstalk path. In addition, the opamp-sharing switches also introduce charge injection and input-dependent resistances. These factors deteriorate both the signal-to-noise ratio (SNR) and the linearity. To alleviate the non-resetting problem, feedback signal polarity inverting (FSPI) is used to alternate the signal polarity, but it can only reduce the opamp offset by 2/3 [2]. To break the crosstalk path, isolation switches are added to tie the parasitic capacitor to ground, and the signal-to-noise-and-distortion ratio (SNDR) is improved by 1-2 dB, but the added switches increase the series resistances and the charge injection [3]. Although opamp current reuse can solve the problems of non-resetting and the crosstalk path by using both NMOS and PMOS input differential pairs in shared opamps, the capacitive level shifter increases the design complexity and the PMOS input differential pair decreases the power efficiency [4].