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This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the proposed AGC is controlled directly by digital bits without conventional extra digital-to-analog converters. The amplifiing function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the efective bandwidth of the AGC. The prototype implemented in a 0.5um n-well CMOS process shows the 32-dB AGC dynamic rage in I/B-dB steps with I73mW at 3V and 25MHz. A two-stage AGC is proposed to reduce power and chip area furthermore.

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