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This brief introduces a low-noise slew-rate/ impedance-controlled high-speed output driver in 0.18-μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and −1.30%, respectively.Index Terms-Electromagnetic interference (EMI), fast compensation, low power, process, voltage, and temperature (PVT) variation detection, slew rate.

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