No abstract

Potassium hydroxide solution was used to etch un-doped GaN grown on the sapphire substrate at 180 and 260°C. We illustrated the etching phenomenon in detail and probed its mechanism in the wet etching process. By multiplying the planar density and the number of dangling bonds on the N atom, we proposed the etching barrier index (EBI) to describe the difficulty degree of each lattice facet. The raking of EBI will be ?cCombining the EBI with SEM results, we thoroughly studied the whole etching process. We confirmed that in our research, KOH wet etching on GaN starts from the r-plane instead of the ?c-plane or -c-plane, which differs from other studies. We also found that during the high-temperature etching process, there are two etching approaches. In one, the etching begins vertically from the top to the bottom, then horizontally, and finally reversely from the bottom to the top. In the other, etching pits will develop into a hexagonal hole of the sidewall of m-plane.

GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

High photovoltage generation from a photoelectrode is important for efficient solar-driven water splitting. Here, we report a thermal treatment process that greatly enhances photovoltage generation from an n-Si/TiO 2 /Ni photoanode. By selectively annealing the TiO 2 interlayer, the photoanode generates a high photovoltage of 570 mV, which is very competitive as compared with photovoltages produced using other similar metal−insulator−semiconductor structures with earth-abundant metal catalysts. Different annealing conditions and junction layer thicknesses were systematically investigated. It is found that the optimal annealing temperature occurs between 500 and 600 °C. Within this temperature range, the deposited amorphous Ti is converted into polycrystalline anatase phase TiO 2 . The optimal annealing time scales linearly with TiO 2 thickness and inversely with annealing temperature. The large photovoltage generation is attributed to the reduced defect states and improved junction barrier height by the annealed TiO 2 interlayer. This study demonstrates that thermal annealing offers an attractive approach to modify the TiO 2 interlayer material's properties for photovoltage optimization.