In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, microarchitecture, architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as "Moore Law". Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the microarchitectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution, out-of-order execution, etc.), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc.). In addition, the paper also discusses microarchitectural techniques likely to be used in the near future such as microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques intended for minimization of power consumption.
In order to organize student mobility program we propose a procedure that enabled us to realize student mobility in a systematic manner. Since our program was not a part of some big international program like Erasmus or Lingua we were forced to establish the procedure based on rules that are in accordance with the Tempus rules for students' travel. For organization and implementation of student mobility program we propose a four-stage procedure. In this paper we describe student mobility program implementation according to the proposed procedure covering preparatory activities, selection procedure, realization of travels and follow-up activities.
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