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This paper proposes a novel implementation propose an improved hybrid CORDIC algorithm, and technique for area optimized direct digital frequency describe an area-optimized VLSI architecture based on the synthesizer (DDFS) based on improved hybrid coordinate algorithm. rotation digital computer(CORDIC) algorithm. ResearchesThe paper is organized in this way: traditional CORDIC at algorithmic level focus on how to reduce algorithm algorithm and its implementation are described in section complexity, such as cutting down all of rotational phase 2.section 3 introduces a novel improved hybrid CORDIC decision circuits and multipliers, simplifying scale factor algorithm with soft-hardware co-design approach. In with soft hardware co-design approach. At architectural section 4, we propose pipeline multilevel loop iteration level, the pipeline multilevel loop iteration implementation architecture for DDFS. Simulation and verification results proposal is adopted for reusing shifting and adder are presented in section 5. Finally, section 6 gives the -subtractor components highly. The design has been conclusions. successfully integrated in a channel demodulation module of broadband network system on chip (SoC) platform.2. Traditional CORDIC Algorithm With generality, the technique can be also applied to other The basic notion of DDFS implementation based on wireless network communication system. traditional CORDIC algorithm is: Through a set of defined Keywords area optimized, improved hybrid CORDIC, linear combinations {wl} to approach the target phase direct digital frequency synthesizer (DDFS), soft-hardware 0 step by step, thereby achieves the aim of frequency co-design synthesize [8]. We usually choose w = arctan(2-')where i1>, and the iterative equations of CORDIC

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