High performance clock synchronization system is essential in communication transmission, which is based on the principle of phase locked loop synchronization that tracking a high accuracy, high stability reference clock source usinh low-pass filter to turn the value into voltage and to control VCO or VXCO and makes the output frequency and the input frequency to maintain strict synchronization.

DC offset of the input analog signal I and Q of quadrature modulator which is as DAC and RF channel interface will affect bit error rate (BER) of the system, the quality of the emission signals and the overall effect of DPD[. This paper focuses on the influences of non-ideal characteristics quadradure modulator on DPD technology.

Digital predistortion (DPD) is a method widely used to compensate the nonlinearity of power amplifier to improve the transmitting signals. The DPD performance, however, depend heavily on the hardware design on signal integrity, EMI and low additional distortion of downconversion circuit. In this paper, a new high-performance hardware solution for DPD is introduced. Engineering tests show that this hardware design characterizes by high reliability and excellent performance to satisfy the requirements of DPD.

As an important module in CMMB system, the performance of phase locked loop will directly determines the accuracy, purity and synchronization of system clock. In this paper, a high performance CPPLL circuit is designed to make each system clock of base station to get strict synchronization in frequency and phase. Test results show that the performance of this design meets the CMMB system requirements

The main disadvantage of multicarrier system is the high peak-to-average power ratio which can easily result in significant cut-the-top distortion of power amplifier. However, the power efficiency of power amplifier will be reduced by power back-off technology. Therefore, crest factor reduction is important in reducing the peak-to-average power ratio of multicarrier system and improving the efficiency of power amplifier. The peak-to-average power ratio can be effectively reduced with small distortion by the algorithm of crest factor reduction based on peak cancellation. And the performance of peak-to-average power ratio is better with the same error vector magnitude.