No abstract

The high-power Asymmetric half-bridge Converter (AHBC) LED constant current driver controlled by digital current mode is a fourth-order system. Static operating point, parasitic resistance, load characteristics, sampling effect, modulation mode and loop delay will have great influence on its dynamic performance. In this paper, the small-signal pulse transfer function of the driver is established by the discrete-time modeling method for the two operating points corresponding to the three modulation modes of the trailing edge, leading edge and double edge. And, the effects of parasitic parameters, delay effect, sampling effect and load effect are fully considered in modeling. For a large number of complex exponential matrix operations, the first order Taylor formula is used for approximate calculation after the coefficient matrix is obtained by substituting the data. Then, Matlab software is used to compare and analyze the discrete-time model and the discrete-average model. The results show that the proposed discrete-time model can more accurately characterize the resonant peak and high-frequency dynamic characteristics, and is very suitable for the design of high frequency digital controller.

In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the seriesload-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input isV and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.INDEX TERMS asymmetric half-bridge; constant-current driver; estimation of duty cycle lost time; predictive quasi-average current mode; digital predictive current-mode control