Cadmium’s (Cd) impact on the photosynthetic activities of energy plant maize was investigated in pot experiments containing different Cd contaminated levels during the whole growth period. The results showed that the ability of photosynthesis was not obviously inhibited by elevated Cd stress. Net photosynthetic rate (NPR) was decreased with the growth of maize, while transpiration rate (TR), stomatal conductance (gs>) and intercellular CO2 concentration (Ci) were enhanced in heading period, then decreased in maturity period. The change of fluorescence quenching and photosystem II (PSII) efficiency was consistent with NPR. Thus, the influence of photosynthesis under Cd stress mainly depended on the response of PSII reaction centre.

In this study, the morphological responses of wheat to Cd during the whole growth stage were investigated in pot experiment with substrates containing 0, 1, 5, 10, 50 and 100 mg Cd/kg soil. The results showed that wheat was moderately tolerant to Cd stress, and the most sensitive endpoint to Cd toxicity was tiller number. The seed germination was not effected by Cd at all concentrations. The No Observed Adverse Effect Concentration (NOAEC) was 10 mg Cd/kg, and the Low Observed Adverse Effect Concentration (LOAEC) was 50 mg Cd/kg for the wheat.

The cadmium (Cd) stress to xylophyta Vitex negundo var. heterophylla including growth responses and Cd accumulation in plant was investigated in pot experiment with different Cd concentrations. The result indicated that the shoot length, shoot diameter and root diameter as well as the biomass of organs were obviously decreased when Cd was 50 mg/kg. 100 mg/kg Cd caused the chlorosis of the leaf. The accumulated ability of Cd in Vitex negundo var. heterophylla in turn was root > leaf > shoot. This plant presented efficient ability in removing the Cd from the contaminated soil when initial Cd in the soil was 20 mg/kg.

The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented. The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter. A new scheme of reload operation is adopted to reduce the propagation delay of the critical path. The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal. The divider is designed in 0.18 um CMOS process. Its division ratio (DR) covers the range from 12 to 127. Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.