0.5-V 5.6-GHz CMOS Receiver Subsystem

Chen, Hsiao-Chin; Wang, Tao; Chiu, Hsien‐Tang; Kao, Tze-Huei; Lu, Shey‐Shi

doi:10.1109/tmtt.2008.2011165

Cited by 16 publications

(3 citation statements)

References 6 publications

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“…An LNA with a low pass filter at 5.6 GHz for the receiver subsystem was reported [22]. The reported LNA gain achieved was 17.1 dB and 8.7 dB of noise level while the power was dissipated at 19.4 mW.…”

Section: Low Noise Amplifier Reviewmentioning

confidence: 99%

High frequency of low noise amplifier architecture for WiMAX application: A review

Ibrahim

Zulkifli

Ariffin

et al. 2021

IJECE

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The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure.

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Section: Low Noise Amplifier Reviewmentioning

confidence: 99%

High frequency of low noise amplifier architecture for WiMAX application: A review

Ibrahim

Zulkifli

Ariffin

et al. 2021

IJECE

View full text Add to dashboard Cite

show abstract

“…In the receiver chain of transceiver Low Noise Amplifier is the important block to further amplify the signal. Objective of this block to amplify the receive signal from antenna without deteriorate in SNR of the LNA and trade off required with other parameters as impedance matching and voltage gain of LNA [3][4]. The basic design principles of an LNA involve maximizing the gain and minimizing the noise figure(NF).…”

Section: Introduction a Background And Motivationmentioning

confidence: 99%

Design Optimization of LNA using PSO algorithm with Multi Stage Noise Matching Technique for UWB Application

Kumar

Kalra

Shukla

2023

Preprint

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This manuscript describe optimization of LNA using PSO algorithms. The proposed LNA consist of two stage cascading. In the first stage current reused technique has been used using complementary MOS. Both the MOS use the common biasing current, henceforth saving a lot of power. While second stage is the cascading of two NMOS transistors, to increase the overall gain. Since traditional method of impedance matching is not sufficient to reduce the Noise Figure(NF). Therefore, an approach aiming to minimize high band noise has been used at the cost of increase in NF minimum. All the passive elements and aspect ratio are optimized through PSO in which objective function consist of NF and voltage gain term. Number of iterations used in PSO algorithm is 1500. LNA is simulated in 45 nm CMOS Technology for a wide range of frequency from 1GHz to 20GHz. Simulation show minimum NF of 1.89 Db, power gain(S21) and input reflection coefficient(S11) 16.8dB and − 19.2dB. Process corner simulation for robust ness of LNA has been done and depicted ten percent variation around the typical value of LNA. The power consumption of 32 mW and chip area order of 2.2mm × 1.6mm with core area is 650 µm in layout design.

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“…The recent and ongoing explosive growth of wireless communication systems require low-cost, low-voltage, and low-power transceivers. To utilize the advantages of scalability and performance (unity current gain cut-off frequency and noise figure), integration of RF and analog circuits with digital circuits in the advanced Complementary Metal-Oxide-Semiconductor (CMOS) technology is promising, even under 0.5 V supply [1,2]. Even using a matured CMOS process, low-voltage operation RF and analog circuits are important and attract some interest, especially in wireless sensor applications with requirements of long battery lifetime.…”

Section: Introductionmentioning

confidence: 99%

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

2019

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This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the standard cell library, thus making the design portable andreducing the time required to fit for different semiconductor processes considerably. Implementedring-DCO has a wide tuning range and high-frequency resolution which meet the demands ofsystem-level integration. The ADPLL implemented in this work has the characteristics of designflexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast responsefor achieving a locked state. The proposed ADPLL can be easily ported to different processes ina short time. The design adaptation cost is limited to adjustment of loop parameters in the code.Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable forSystem-on-Chip (SoC) applications.

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0.5-V 5.6-GHz CMOS Receiver Subsystem

Cited by 16 publications

References 6 publications

High frequency of low noise amplifier architecture for WiMAX application: A review

High frequency of low noise amplifier architecture for WiMAX application: A review

Design Optimization of LNA using PSO algorithm with Multi Stage Noise Matching Technique for UWB Application

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

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