1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Li, Jing; Montoye, Robert K.; Ishii, Masatoshi; Chang, Leland

doi:10.1109/jssc.2013.2292055

Cited by 145 publications

(94 citation statements)

References 15 publications

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“…Memory-based computing has been shown significant energy efficiency for emerging non-CMOS memories which are particularly well-suited for dense non-volatile memory design [10,12,13]. For example, spin-torque transfer RAM (STTRAM) has been used for reconfigurable frameworks which partition the entire input application into smaller representable partitions using lookup tables (LUTs) [12], or use co-design approach for a better application mapping [13].…”

Section: Related Workmentioning

confidence: 99%

“…In the second stage, a 1T-1R memristive memory is used to return the pre-stored output result in case of a match. For TCAM design, we use a memristive 2T-2R cell structure proposed in [10]. Each line in the TCAM stores one set of the frequent input operands, and each bit-cell consists of two memristive element to store the pattern and two access transistors, as shown in Fig.…”

Section: Associative Memristive-based Computingmentioning

confidence: 99%

“…In case of a match for a line, the ML is not connected to the ground because of the high-resistance memristive devices and stays at the precharged value for a longer time, providing a clear margin. A clocked self-referenced sensing scheme as well a 2-bit encoding is also applied to further increase the noise margin [10], and provide digital match/mismatch outputs that are fed to the next stage as the enable lines (EnL) which display a one-hot encoding; therefore the hit signal is the logical OR of EnLs.…”

Section: Associative Memristive-based Computingmentioning

confidence: 99%

“…To avoid its read disturbance challenge, reliable read operation techniques are proposed [9,8], including a process-temperature-aware dynamic bitline bias scheme on a 4-Mb memristor fabricated chip [8]. Li et al demonstrate a 1-Mb ternary content addressable memory (TCAM) test chip using 2-transistor/2-resistive-phase-change-storage (2T-2R) cells [10]. It achieves > 10× smaller cell size than SRAM-based TCAMs, and ensures reliable low-voltage search operation in the presence of PVT variations thanks to a clocked self-referenced sensing scheme [10].…”

Section: Introductionmentioning

confidence: 99%

“…Li et al demonstrate a 1-Mb ternary content addressable memory (TCAM) test chip using 2-transistor/2-resistive-phase-change-storage (2T-2R) cells [10]. It achieves > 10× smaller cell size than SRAM-based TCAMs, and ensures reliable low-voltage search operation in the presence of PVT variations thanks to a clocked self-referenced sensing scheme [10].…”

Section: Introductionmentioning

confidence: 99%

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Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Rahimi¹,

Ghofrani²,

Lastras-Montaño³

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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Thousands of deep and wide pipelines working concurrently make GPGPU high power consuming parts. Energy-efficiency techniques employ voltage overscaling that increases timing sensitivity to variations and hence aggravating the energy use issues. This paper proposes a method to increase spatiotemporal reuse of computational effort by a combination of compilation and micro-architectural design. An associative memristive memory (AMM) module is integrated with the floating point units (FPUs). Together, we enable finegrained partitioning of values and find high-frequency sets of values for the FPUs by searching the space of possible inputs, with the help of application-specific profile feedback. For every kernel execution, the compiler pre-stores these high-frequent sets of values in AMM modules -representing partial functionality of the associated FPU-that are concurrently evaluated over two clock cycles. Our simulation results show high hit rates with 32-entry AMM modules that enable 36% reduction in average energy use by the kernel codes. Compared to voltage overscaling, this technique enhances robustness against timing errors with 39% average energy saving.

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Section: Related Workmentioning

confidence: 99%

Section: Associative Memristive-based Computingmentioning

confidence: 99%

Section: Associative Memristive-based Computingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Rahimi¹,

Ghofrani²,

Lastras-Montaño³

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

View full text Add to dashboard Cite

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Nonvolatile Logic and Ternary Content‐Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors

et al. 2021

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Hardware realization of in‐memory computing for efficient data‐intensive computation is regarded as a promising paradigm beyond the Moore era. However, to realize such functions, the device structure using traditional Si complementary metal–oxide–semiconductor (CMOS) technology is complex with a large footprint. 2D material‐based heterostructures have a unique advantage to build versatile logic functions based on novel heterostructures with simplified device footprint and low power. Here, by adopting the charge‐trapping mechanism between a black phosphorus (BP) channel and a phosphorus oxide (POx) layer, a nonvolatile CMOS logic circuit based on 2D BP and rhenium disulfide (ReS2) with a high voltage gain of ≈275 is realized with a persistent hysteresis window. A Schmidt‐like flip‐flop using only two transistors is also demonstrated, with far fewer transistor numbers than the conventional silicon counterpart, which usually requires six transistors. Furthermore, four‐transistor (4T) nonvolatile ternary content‐addressable memory (nvTCAM) cells are demonstrated with far fewer transistors for parallel data search. The nvTCAM cells exhibit high resistance ratios (Rratio) up to ≈103 between match and mismatch states with zero standby power thanks to the nonvolatility of the BP transistors. This back‐end‐of‐line compatible nvTCAM shows advantages over other structures with reduced complexity and thermal budget.

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Ferroelectric Transistors for Memory and Neuromorphic Device Applications

Kim

Lee

2023

Advanced Materials

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Because a non-centrosymmetric crystal structure is mandatory for ferroelectric properties, very few materials are classified as ferroelectric. Historically, materials with complex crystal structures, such as BaTiO 3 (BTO), Pb[Zr x Ti 1−x ]O 3 (PZT), and Sr 2 Bi 2 TaO 9 (SBT), have been found to exhibit ferroelectricity. [5][6][7][8][9] Due to their spontaneous polarization, ferroelectric materials are diversely applied in memory devices, actuators, sensors, and energy storage. [1,2,[10][11][12][13] As the polarization state of ferroelectric materials can be regulated by an external electric field and the polarization is retained after the removal of the external electric field, such materials have the potential for applications involving high-performance non volatile memories. [9,14] However, some issues of conventional ferroelectric materials, such as high annealing temperatures, the requirement of noble electrode materials, and the diffusion of elements such as Pb complicate the integration of the previously reported ferroelectric materials into complementary metal-oxide semiconductors (CMOSs). [15][16][17][18] Furthermore, the large dielectric constants of perovskite-based ferroelectrics lead to high depolarization fields; [9,16] thus, the materials have short retention time and exhibit unstable polarization. [9] Additionally, the limited thickness scalability, complex etching process, and fatigue behaviors of perovskite-based ferroelectrics hinder the development of highly scaled ferroelectric devices. [9,18] Thus, semiconductor devices based on ferroelectric materials have limited commercial applications. Since the development of hafnia-based ferroelectrics, ferroelectric hafnia has attracted immense attention toward the development of semiconductor devices. [19][20][21] Compared to perovskite-based ferroelectric materials, hafnia-based ferroelectrics exhibit high scalability, and have high coercive electric fields (E c ) and low dielectric permittivity values, making them suitable for the fabrication of high-performance memory devices. [2,16,20,22] Additionally, hafnia is compatible with Si-based CMOS processes. Due to these advantages, hafnia-based ferroelectrics have been used in next-generation memory devices (such as ferroelectric capacitors, transistors, and tunnel junctions [FTJs]). [22][23][24][25][26] This paper reviews the recent findings and applications of hafnia-based ferroelectrics, highlighting the recent advances in ferroelectric transistors for next-generation memory and neuromorphic Ferroelectric materials have been intensively investigated for highperformance nonvolatile memory devices in the past decades, owing to their nonvolatile polarization characteristics. Ferroelectric memory devices are expected to exhibit lower power consumption and higher speed than conventional memory devices. However, non-complementary metal-oxidesemiconductor (CMOS) compatibility and degradation due to fatigue of traditional perovskite-based ferroelectric materials have hindered the development of high-density...

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1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Cited by 145 publications

References 15 publications

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Nonvolatile Logic and Ternary Content‐Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors

Ferroelectric Transistors for Memory and Neuromorphic Device Applications

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