2.4–3.2 GHz robust self-injecting injection-locked phase-locked loop

Abstract

In this paper, we propose a robust self-injecting injection-locked phase-locked loop (SI-ILPLL). It adopts a phase alignment loop (PAL) based on a subsampling phase frequency detector to align the phase between the injected pulse and the voltage-controlled oscillator (VCO) output. With the proposed phase frequency detector, the PAL performs phase alignment and the pulse generator can self-inject pulses into the VCO for injection locking. The subsampling phase detection and self-injection locking techniques can suppress the phase noise of the SI-ILPLL. The SI-ILPLL shows excellent robustness to environmental interference. The SI-ILPLL is implemented in 65 nm CMOS technology. It occupies an active area of 0.7 mm 2 . The measured root-mean-square (RMS) jitters at 3.2 GHz output without and with injection locking are 216 and 131 fs, respectively. When the supply voltage varies from 1.17 to 1.23 V and the temperature varies from 0 to 80 °C, the maximum jitter variation of all the output frequencies is less than 50 fs. The measured results demonstrate that even when a large interference appears at the supply voltage and unlocks the SI-ILPLL, the SI-ILPLL can self-recover its injection-locked state rapidly after the disturbance disappears, whereas the conventional ILPLL cannot self-recover its locked state after losing it. The power consumption of the SI-ILPLL is 7.4 mW under a 1.2 V supply voltage. The SI-ILPLL achieves a figure of merit (FOM) of %249 dB.