20-Bit RISC and DSP System Design in an FPGA

Tomar, Amit Kumar Singh; Jain, Rita

doi:10.1109/mcse.2013.20

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…In main memory, memory address used as an index and in cache a portion of memory address is used as an index. Thus the register bank was made up of BRAM [ 7 ].…”

Section: G) Register Bankmentioning

confidence: 99%

Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

Divya¹,

Balasaraswathi²,

R³

et al. 2020

IJEAT

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The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture

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“…In main memory, memory address used as an index and in cache a portion of memory address is used as an index. Thus the register bank was made up of BRAM [ 7 ].…”

Section: G) Register Bankmentioning

confidence: 99%

Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

Divya¹,

Balasaraswathi²,

R³

et al. 2020

IJEAT

View full text Add to dashboard Cite

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“…For the full fill of demand Khazaee et al [7] have presented a Java programming language as Java virtual machine (JVM), but the given JVM is not enough capacity in speed or storage. The problem of low speed and memory overhead is carried out by Tomar et al [8] in which discussed the working progress of RISC with the connecting of the digital signal processor (DSP) it can perform effectively in several operations.…”

Section: Related Workmentioning

confidence: 99%

Implementation and Verification of Risc Processor on Fpga Using Chipscope Pro Tool

Divakaran¹,

N²,

S³

et al. 2019

IJCESR

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The advanced microprocessors are widely used for most of the complex systems. A silicon chip of fingernail-size may exhibit entire high performance guaranteed processor, higher cache memory and logic needed for interfacing with external devices. Reduced Instruction Set Computing (RISC) is a CPU (Central Processing Unit) design mechanism based on the vision in which exhibits basic instruction set and yields better performance after comparison with microprocessor architecture and it has the capacity to perform the instructions through microprocessor cycles per instruction. In this paper, the Cost-effective and efficient RISC Processor is designed. The RISC Processor design includes Fetching, decoding, Data and instruction memory, and Execution units. The Execution unit contains ALU (Arthematic and Logical Unit) Operations. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device and the physically debugging of the RISC Processor, and ALU Units are verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the RISC Processor is made concerning previous similar architecture with improvements.

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