22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

Abstract

a b s t r a c tThe Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC's 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from þ 5.14/ À1 LSB to þ 1.27/ À 0.92 LSB, and improved the INL error from þ 5.35/À 5.34 LSB to þ 3.17/À 3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.& 2015 Elsevier Ltd. All rights reserved. MotivationColumn-parallel ADCs are frequently used in CMOS imagers to achieve fast frame rates. The key parameters for the design of these ADCs include area, pitch, speed, and quantization resolution. The single-slope architecture is often used because of the simple circuitry in each channel. But the conversion rate for this type of ADC is usually less than 1 MSPS, because the full-scale conversion time doubles with each additional bit [1,2]. In comparison, successive approximation register (SAR) ADCs can perform faster conversions at moderate to high resolution because the conversion time scales linearly with the number of bits. The disadvantage of SAR ADCs, however, is that they rely on a DAC to produce reference voltages. Usually a high-resolution high-linearity SAR ADC requires a large silicon area for capacitors in the DAC, making it unsuitable for column-parallel applications.One way to mitigate the large area requirement of SAR ADCs is to use the subranging technique. First a coarse conversion is performed to determine the M most significant bits. Then a fine conversion is performed over the subrange determined by the coarse conversion to calculate the K least significant bits. One way of implementing this second conversion is using a capacitor-array DAC to resolve voltages between two reference voltages that are generated with a resistor ladder [3]. When building an array of column-parallel ADCs, this resistor ladder can be shared by all of the channels. The area can be further reduced by using the same capacitor-array DAC to perform both the coarse and fine conversions, but in order to guarantee a correct coarse conversion for any inputs, the DAC must be accurate to the full resolution of the conversio...