2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement

Ishikawa, Ryota; Tawada, Masashi; Yanagisawa, Masao; Togawa, Nozomu

doi:10.1109/ngcas.2018.8572289

Cited by 1 publication

(1 citation statement)

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“…The only limitation of this proposal is that this SN duplicator has larger circuit area than those of the other SN duplicators, still very small compared with * 1 The preliminary version of this paper appeared in Ref. [9]. c 2020 Information Processing Society of Japan those of binary computing, even with the random number generators to generate SNs.…”

Section: Proposalmentioning

confidence: 99%

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design

Ishikawa

Tawada

Yanagisawa

et al. 2020

IPSJ Transactions on System LSI Design Methodology

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Stochastic computing is a computation method which can implement arithmetic operations by simple logic circuits. Stochastic numbers are used in this method, whose values are defined by their bit streams' appearance rates of 1's. As a nature of stochastic computing, changing the length of the input stochastic numbers will change the whole circuit's accuracy. However, in some implementations with re-convergence paths, the circuit itself will cause errors, i.e., the length of the input stochastic numbers does not change that circuit's accuracy. This paper proposes a stochastic number duplicator whose outputs differ every time and are all independent. This stochastic number duplicator has a scalable structure by changing the numbers of flip-flops for bit re-arrangement. From the experimental evaluations and discussions, we clarify that the proposed stochastic number duplicator enables accuracy-flexible circuits. interests are combinatorics and graph theory, computational geometry, VLSI design and verification, and network analysis and design. He is a member of IEEE, ACM, IPSJ, and IEICE.

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Section: Proposalmentioning

confidence: 99%