3-bit, 8 GSPS flash ADC

Baringer, C.; Jensen, J.F.; Burns, L.; Walden, Bob

doi:10.1109/iciprm.1996.491935

Cited by 20 publications

(13 citation statements)

References 5 publications

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“…This ADC is thus inherently fast. The fastest ADC reported is the 3-bit, 8 Gs/s Nyquist flash converter [5] cited above. This ADC had a maximum sampling rate of 14 Gs/s.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

“…Aside from quantization noise, three mechanisms limit achieved SNR: input-referred circuit noise (equivalent thermal noise), aperture uncertainty, and comparator ambiguity. The equations that calculate the associated maximum achievable resolutions, in SNR-bits, are thermal noise (referred to the input: (5) aperture uncertainty: (6) comparator ambiguity: (7) Fig. 7.…”

Section: Performance Analysismentioning

confidence: 99%

“…This is related to the unitycurrent-gain frequency of the transistors employed in the circuit. An analysis of the flash ADC in [5] indicated that [8]. From these expressions SNR curves are calculated for values of input-referred thermal noise, aperture jitter, and which measures comparator ambiguity.…”

Section: Performance Analysismentioning

confidence: 99%

“…Comparator ambiguity is limited via the regeneration time constant corresponding to a value of GHz for ADC's at the highest sampling rates. The 3-bit, 8 Gs/s Nyquist ADC [5] was fabricated with an GHz InP process. The aperture uncertainty results in the bit/octave slope; this is the dominant factor because the range of affected values is so large.…”

Section: Performance Analysismentioning

confidence: 99%

“…This is indicated by the state-of-the-art line on the graph. Second, the highest Nyquist sampling rate attained is 8 giga samples per second (Gs/s) [5]. An analysis of SNR shows that the 1-bit per octave slope is related to the sample-to-sample variation of the instant in time at which sampling occurs.…”

Section: Introductionmentioning

confidence: 99%

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Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,839

959

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Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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“…This ADC is thus inherently fast. The fastest ADC reported is the 3-bit, 8 Gs/s Nyquist flash converter [5] cited above. This ADC had a maximum sampling rate of 14 Gs/s.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

Section: Performance Analysismentioning

confidence: 99%

Section: Performance Analysismentioning

confidence: 99%

Section: Performance Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,839

959

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New submicron HBT IC technology demonstrates ultra-fast, low-power integrated circuits

Hafizi

1998

IEEE Trans. Electron Devices

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High-frequency low-power ICs in a scaled submicrometer HBT technology

Hafizi

1997

IEEE Trans. Microwave Theory Techn.

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Fast, dense, and low-power integrated circuits (IC's) have been developed using a new scaled heterojunction bipolar transistor (HBT) IC process. HBT's have been fabricated with emitter dimensions of 0.3 m 2 and a circuit metallization pitch of 4 m to reduce power and compact the chip size. Submicrometer HBT's exhibited f T of over 160 GHz. A number of circuits using this new technology have been demonstrated, including a low-power comparator test chip clocked at 40 GHz and an ultra-low-power phase-locked-loop-based (PLL) clock and datarecovery circuit consuming 22-mW dc power at 4 GHz.

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3-bit, 8 GSPS flash ADC

Cited by 20 publications

References 5 publications

Analog-to-digital converter survey and analysis

Analog-to-digital converter survey and analysis

New submicron HBT IC technology demonstrates ultra-fast, low-power integrated circuits

High-frequency low-power ICs in a scaled submicrometer HBT technology

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