3D RESURF double-gate MOSFET: Arevolutionary power device concept

Udrea, F.; Popescu, A.; Milne, W. I.

doi:10.1049/el:19980504

Cited by 73 publications

(12 citation statements)

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“…For both devices, breakdown occurs at the n+ injector layer at the cathode, but the presence of the SJ pillars alters the electric field distribution such that a larger voltage can be supported for a given device thickness. As a result, a SJ device can be made thinner for the same breakdown voltage to improve on-state performance, in line with previous studies [7], [9], [18]. Fig.…”

Section: Introductionsupporting

confidence: 87%

Investigation of the Dual Implant Reverse-Conducting SuperJunction Insulated-Gate Bipolar Transistor

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Udrea

Antoniou

2019

IEEE Electron Device Lett.

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This letter presents the Dual Implant SuperJunction (SJ) trench Reverse-Conducting (RC) Insulated Gate Bipolar Transistor (IGBT) concept with two implanted SJ pillars in the drift region; one from the cathode side and another from the anode side. The proposed device is compatible with current manufacturing processes and enables a full SJ structure to be achieved in a 1.2kV device as alignment between the pillars is not required. Extensive Technology Computer Aided Design (TCAD) simulations have been performed and demonstrated that utilising this dual implantation technique can result in a 77% reduction in turn-off losses for a full SJ structure, compared to a conventional RC-IGBT. The results show that any snapback in the on-state waveform significantly increases the turn-off losses and only a deep SJ device (pillar gap < 10μm) warrants the additional processing expense. 

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Section: Introductionsupporting

confidence: 87%

Investigation of the Dual Implant Reverse-Conducting SuperJunction Insulated-Gate Bipolar Transistor

Findlay

Udrea

Antoniou

2019

IEEE Electron Device Lett.

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“…This is the Super Junction (SJ) concept, which was proposed during the 1990s [3][4][5]. The SJ concept can be used to significantly reduce the resistance of the drift region in high-voltage Vertical Double-diffused MOS (VDMOS) or LDMOS for a given BV [6][7][8][9][10][11]. The typical crosssection of SJ-VDMOS and SJ-LDMOS can be seen in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

A Review of Super Junction LDMOS

et al. 2011

IETE Tech Rev

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Super Junction Lateral Double-diffused MOSFET (SJ-LDMOS) is one of the important attractive devices in high-voltage integrated circuit and power integrated circuit. However, the SJ-LDMOS is generally implemented on a low-resistance substrate, which always suffers from substrate-assisted depletion (SAD) effect, which thus degrades the performance of devices. A number of literatures have been published to solve the SAD effect and improve performance. This review summarizes the developments made in SJ-LDMOS based on bulk silicon, silicon on insulator, and silicon on sapphire in the last 10 years. Finally, the future work what researchers can do on the SJ-LDMOS also has been proposed.

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“…1.2kV). The new termination is based on employing the 3D Resurf concept earlier reported in [5] for lateral high volt age devices.…”

Section: In [4] An Interesting Vertical J T E Termination Basedmentioning

confidence: 99%

“…The 3D-Resurf concept [5] is similar to the superjunction concept [6,7] but has been specifically thought for lateral high voltage devices.…”

Section: The 3d-resurf Conceptmentioning

confidence: 99%

“…Due to this twodimensional spreading of the electric field at the surface of the termination area, the shape of the electric field between two p+ floating rings is no longer triangular, which is the case for a standard floating ring termination, but 'more' rectangular (Fig. 3), as in an in-trinsic layer [5]. Thus, the voltage supported between each pair of floating p+ rings, since it is equivalent to the area under the electric field distribution, is significantly higher than in the standard FR termination.…”

Section: The 3d-resurf Termination Structurementioning

confidence: 99%

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