4670‐PPI OLEDoS pixel circuit design for wide data voltage range in a 5 V 0.13 μm CMOS process

Abstract

OLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4670‐PPI OLEDoS display while considering current uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40 × 120 pixel arrays fabricated in a 5 V 0.13 μm CMOS process.