65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

Abstract

In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitttrigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I onto -I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40-60% and 30-50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to subthreshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.