8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS

Abstract

Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1][2][3][4][5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes.In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offsetcancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil f T -doubler output buffer. The block diagram and experimental setup are shown in Fig. 8.4.1. The capacitance of the off-chip GaAs PIN photodetector (PD), which is wire-bonded to the CMOS receiver, is 100fF with 0.4A/W responsivity. The two optical receivers have identical designs except for the LA, in which two different inductive peaking techniques, conventional and sharedinductor, are designed and fabricated on the same die in 28nm CMOS technology. Figure 8.4.2 shows the circuit schematics of the pseudo-differential CMOS pushpull TIA with series-peaking inductors. The CMOS push-pull TIA has good signal gain and input-referred noise at low supply voltage because of current re-use of NMOS and PMOS [4]. Compared with CMOS inverter TIA in [4], the presented TIA employs a current tail to make the g m of M1~M4 refer to the bias current instead of the supply voltage for better supply noise rejection. In order to provide better single-ended to differential conversion for LA input, we include the crosscoupled pair M 7 and M 8 , which act as common-source amplifiers to provide negative voltage gain through the feedback resistor R F . The pseudo-differential configuration of the TIA provides better supply-noise rejection as well as jitter performance than the singled-ended TIA. The simulated gain of TIA is 46dBΩ and the input-referred noise is 2.5μA rms with 20GHz BW. The DC-offset cancellation circuit in Fig. 8.4.2 receives pseudo-differential outputs from the TIA and adjusts the output DC levels for the LA, based on the offset voltage provided by the LPF as shown in Fig. 8.4.1.Circuit schematics of LAs using both conventional and shared-inductor peaking are shown in Fig. 8.4.2. For the LA using conventional inductive peaking, two inductors L 1 are required for each stage. On the other hand, the LA using sharedinductor peaking requires only two inductors L 2 for every two adjacent stages, wherein the inductance value of L 2 is half of L 1 . The reason that L 2 can be only half of L 1 is because by sharing the inductor L 2 between two adjacent stages, the in-phase current...

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

“…VCSEL diodes operating in the 1.3 μm wavelength have currently a limited commercial availability, thus other transmission systems with optical modulators need to be used which can be challenging especially in mobile systems. This is the reason for this work, as well as [1], [3] and [12] focus on 850 nm systems.…”

A CMOS Low-Power Cross-Coupled Immittance-Converter Transimpedance Amplifier

“…Assuming the frequency response is designed without any peaking ( ), the 3 dB bandwidth is bounded by . Using in (3) and following the procedure in [9] results in a transimpedance limit of (4) 1 If and are used in the TIA analysis, then .…”

“…Various techniques have been proposed to relax this bandwidth limitation and improve the maximum possible transimpedance gain, i.e., transimpedance limit. For example, inductive-peaking TIAs [1], [2] and regulated-cascode TIAs and their modifications [3]- [6] are widely used to enhance receiver bandwidths.…”

100 Gb/s photoreceiver module based on 4ch × 25 Gb/s vertical-illumination-type Ge-on-Si photodetectors and amplifier circuits

“…Recently, there has been remarkable progress in Ge-on-Si photodetectors (Ge PDs) [14][15][16][17][18][19][20][21][22][23][24][25][26], which are the main active components in silicon optical receivers, and also in CMOS ICs for optical/electrical (O/E) interface and all-silicon photonic/CMOS receivers [6][7][8][9][28][29][30][31][32][33][34]. There have been reports on silicon photonic receivers where Ge waveguide (WG) PDs on SOI substrates and CMOS Rx ICs were monolithic-or hybrid-integrated [2,[28][29][30][31][32][33][34][35][36].…”

“…There have been reports on silicon photonic receivers where Ge waveguide (WG) PDs on SOI substrates and CMOS Rx ICs were monolithic-or hybrid-integrated [2,[28][29][30][31][32][33][34][35][36]. In general, most of reported Ge PDs are waveguide-type defined on SOI [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][25][26][27][28][29][30][31][32][33][34], whereas most of CMOS ICs are based on bulk silicon technology. On the other hand, vertical-illumination Ge PDs are defined on bulk silicon [6,9,22,[24][25][26], and are of interest since they can enable the monolithic integration with bulk CMOS ICs more realistic, and have a big advantage in packaging with optical fiber.…”