9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation

Power amplifier design for next generation WLAN

“…Another method to improve the efficiency at large power back-off is the digital PA (DPA), in which the PA is divided into many small PA units, and each unit is designed as a switching-typed PA controlled digitally for their ON and OFF. State-of-the-art DPAs were reported in [21] and [22] It is no doubt that reported PAs for WLAN at the 2.4GHz and 5GHz bands have achieved superior performance. Designing of PAs separately for these two frequency bands makes it easier to optimize the performance for each band, however, it would consume less chip area, and therefore lower cost, if a wideband PA can be designed to support both of these two frequency bands.…”

“…Considering the capacitance (including parasitic) at transistor drain output, the load impedances at the 3 rd and above harmonics can be close to short circuits as well. Therefore, the matching technique described in Chapter 4 can be further extended and used to design wideband PAs in inverse Class-D. As CMOS technology develops, integrated inverse Class-D PAs are able to achieve higher and higher efficiency and can be used as unit cells to construct digital PAs for WLAN at the 2.4GHz and 5GHz bands [21,22,118]. When compared to PAs in Class-AB, digital PAs have higher efficiency, especially at a large power back-off.…”

“…The other chip for WLAN at 60GHz utilizes single-carrier modulation, featuring a maximum data-rate of 4.6Gbps which is more than 10 times faster than that of the chip at 2.4GHz and 5GHz. Similar to many other publications/products[14][15][16][17][18][19][20][21][22], the chip for WLAN at 2.4GHz and 5GHz contains separate RF circuits for each band CHAPTER 1 5…”